| 摘要 |
<p>PURPOSE: To provide a high-speed synchronizer which can easily realize such a high-density circuit technique as the VLSI with a simple circuit configuration and can easily and quickly fixe input data signals to a local clock signal. CONSTITUTION: This high-speed digital data synchronizer is incorporated with a local oscillator 10, a delaying element line 11, and clock phase selecting means 14, 15, 16, 17, and 18, generates the catching timing of a phase waveform generated from the oscillator 10 and line 11 by using data input signals and the bit pattern corresponding to the caught phase waveform synchronous to the data signals from a transition detector 13, and controls the storage of waveform discriminating data when a new synchronous waveform is out of a two-bit window or the selection of the new synchronous waveform when a synchronous pattern does not change during the N continuous periods of the input data signals by means of a control means which is clocked by the input data signals.</p> |
