发明名称 |
Methods of forming electrical interconnects using electroless plating techniques that inhibit void formation |
摘要 |
Methods of forming electrical interconnects include forming a copper pattern on a semiconductor substrate and then forming an electrically insulating capping layer on the copper pattern and an interlayer insulating layer on the electrically insulating capping layer. A contact hole is then formed, which extends through the interlayer insulating layer and the electrically insulating capping layer and exposes an upper surface of the copper pattern. An electroless plating step is then performed to form a copper pattern extension onto the exposed upper surface of the copper pattern. The copper pattern extension may have a thickness that is less than a thickness of the electrically insulating capping layer, which may be formed as a SiCN layer.
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申请公布号 |
US7879720(B2) |
申请公布日期 |
2011.02.01 |
申请号 |
US20080241744 |
申请日期 |
2008.09.30 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD.;INFINEON TECHNOLOGIES AG |
发明人 |
JANG WOO JIN;CHO SUNG DONG;KIM HYUNG WOO;MOON BUM KI |
分类号 |
H01L23/52;H01L21/768 |
主分类号 |
H01L23/52 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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