发明名称 |
Two Partition Accelerator and Application of Tiered Flash to Cache Hierarchy in Partition Acceleration |
摘要 |
An approach is provided to identify a disabled processing core and an active processing core from a set of processing cores included in a processing node. Each of the processing cores is assigned a cache memory. The approach extends a memory map of the cache memory assigned to the active processing core to include the cache memory assigned to the disabled processing core. A first amount of data that is used by a first process is stored by the active processing core to the cache memory assigned to the active processing core. A second amount of data is stored by the active processing core to the cache memory assigned to the inactive processing core using the extended memory map.
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申请公布号 |
US2011022803(A1) |
申请公布日期 |
2011.01.27 |
申请号 |
US20090508621 |
申请日期 |
2009.07.24 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
FLEMMING DIANE GARZA;MARON WILLIAM A.;RAGHAVAN RAM;SRINIVAS MYSORE SATHYANARAYANA;VAIDYANATHAN BASU |
分类号 |
G06F12/08;G06F12/00 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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