| 摘要 |
FIELD: physics, computer engineering. ^ SUBSTANCE: invention can be used in digital computer engineering and in computer processors and digital automation devices. In the method, first and second elementary operations (EO) for logical multiplication (LM) are performed in a first time step TS1, the results of which are used to create a unit lending potential (LP) in high-order bits, the LM2 code is received in a second register B and the register flip-flops A are set to zero for unit code bits of the minuend and the subtrahend. In the second TS2, an EO for modulo 2 addition of the code Ai with LP from the least significant bit or code Bi is performed. Is said signals are present in the i-th bit, simultaneous modulo 2 addition is prohibited. The difference sign is also formed in TS2 and the LP from the most significant bit is recorded. If LP=0, i.e. when |A|>]B|, the operation is completed. If LP=1, i.e. |A|<|B|, the code of register A is inverted on TS3, 4 with addition of one to the least significant bit of the device. The device has AND elements, OR elements, digital inverters, RS flip-flops and control inputs. ^ EFFECT: faster subtraction owing to merging the time for performing the elementary operation for receiving the subtrahend and creating the lending potential. ^ 2 cl, 2 dwg, 1 tbl |
