发明名称 |
Semiconductor integrated memory manufacturing method and device |
摘要 |
A method of manufacturing a semiconductor integrated memory device including a plurality of a memory cells, and the semiconductor memory device, wherein each memory cell includes a transistor and a capacitor. The capacitor is formed of first and second electrodes and a dielectric layer. The first electrode and the dielectric layer are successively formed on a main surface of a semiconductor substrate by epitaxial growth. A region of the capacitor is removed to expose a region of the main surface of the substrate under the capacitor. A single crystal semiconductor layer is formed on the exposed region of the substrate by epitaxial growth, and the transistor is formed on the single crystal semiconductor layer, thereby to obtain a device having high integration density integration and preferred performance with high yield.
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申请公布号 |
US6165837(A) |
申请公布日期 |
2000.12.26 |
申请号 |
US19990276727 |
申请日期 |
1999.03.26 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
KAWAKUBO, TAKASHI;FUKUSHIMA, NOBORU |
分类号 |
H01L21/8247;H01L21/8242;H01L21/8246;H01L27/10;H01L27/105;H01L27/108;H01L27/12;H01L29/788;H01L29/792;(IPC1-7):H01L21/824 |
主分类号 |
H01L21/8247 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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