发明名称 Logic synthesis method and semiconductor integrated circuit
摘要 A semiconductor integrated circuit of registers and combinational logic circuits connected between the registers is generated by a top-down design technique. When performing the logic synthesizing of such a semiconductor integrated circuit by making use of data of register transfer level, a combinational logic circuit with a critical path is driven with power from a high-voltage source, a combinational logic circuit without a critical path is driven with power from a low-voltage source, and a level converter capable of converting an input signal of low voltage level into a high-voltage-level output is arranged in a register located upstream of a combinational logic circuit with a critical path. Compared with a technique in which only critical paths are driven with power from a high-voltage source, it becomes easier to determine where to arrange level converters. Additionally, the number of level converters required can be reduced, thereby facilitating design work. Each combinational logic circuit with a critical path is driven by the high-voltage source, so that the power consumption increases in comparison with a case where only critical paths are driven by the high-voltage source. However, the ratio of the number of combinational logic circuits with a critical path to the total number of combinational logic circuits contained in the whole semiconductor integrated circuit is negligible, and other combinational logic circuits without a critical path are driven by the low-voltage source. The entire power consumption of the semiconductor integrated circuit can be reduced.
申请公布号 USRE37475(E1) 申请公布日期 2001.12.18
申请号 US19980076703 申请日期 1998.05.13
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 OHARA KAZUTAKE
分类号 G06F17/50;(IPC1-7):H01L25/00;H03K19/177 主分类号 G06F17/50
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