发明名称
摘要 <p>Disclosed is the hardware construction of a radio communication apparatus that can meet advanced radio communications. A control bus for transferring control signals between a main processor and components is separated from a data bus for transferring transmission/receive signals between processor units including sub-processors and an external interface. The sub-processors constitute the processor units, and a software defined radio of the present invention may include plural processor units. The processor units are connected by a dedicated interunit interface. The processor units may include multiple sub-processors, which are connected serially through an interprocessor interface.</p>
申请公布号 JP4617782(B2) 申请公布日期 2011.01.26
申请号 JP20040253730 申请日期 2004.09.01
申请人 发明人
分类号 G06F13/36;G06F13/38;H04B1/38;H04B7/26;H04M1/00;H04M11/00 主分类号 G06F13/36
代理机构 代理人
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