| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock recovery circuit which does not easily cause out-of-synchronism even when excessive phase noise is detected. <P>SOLUTION: The clock recovery circuit having a PLL circuit comprising a phase comparator circuit, a filter and a voltage controlled oscillation circuit is provided with: a signal generation circuit for detecting a phase difference exceeding ±π between data signals and clock signals outputted from the voltage controlled oscillation circuit by using a pattern included in inputted data signals and for generating signals corresponding to the phase difference; and a circuit for adding the signals to output signals from the phase comparator circuit. <P>COPYRIGHT: (C)2008,JPO&INPIT |
