| 摘要 |
Equal numbers of variable capacitance elements, capacitance values of which are separately controlled according to a logic value of a corresponding bit of a delay control signal that is in a one-to-one relation with an oscillation frequency, are connected in parallel among differential outputs of all delay circuits excluding a differential non-inverting delay circuit at the end, which extracts a frequency signal to the outside. Bits of the delay control signal are connected in a one-to-one relation to the equal numbers of variable capacitance elements arranged on output sides of all the delay circuits, in a relation in which delay control signals continuous in terms of frequency are not connected to the equal number of variable capacitance elements arranged on an output side of one of the delay circuits.
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