发明名称 PLL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a PLL circuit in which dead time within a loop is compensated for and thus desired characteristics can be obtained.SOLUTION: A main path 110 includes: a phase detector 111 arranged at an input stage to perform phase detection between an input signal and an actual signal; a loop filter 113 arranged on the output side of the phase detector to determine response characteristics of the loop, and a controlled oscillator 114 which oscillates at a frequency corresponding to the output signal of the loop filter, and outputs an oscillation signal to a main feedback path as the actual signal. The local feedback path 130 includes a replica part 131 to which output of the loop filter is input and which functions as the replica of the controlled oscillator, a delay part 132 which delays output of the replica part by one round dead time, a first subtractor 133 which obtains difference between the input signal and the output signal of the delay part, and a second subtractor 136 which subtracts a signal obtained by multiplying an internal signal in the loop filter by a constant value from the output signal of the first subtractor and outputs a resulting signal to the input side of the loop filter.
申请公布号 JP2011015167(A) 申请公布日期 2011.01.20
申请号 JP20090157256 申请日期 2009.07.01
申请人 SONY CORP 发明人 GENDAI YUUJI
分类号 H03L7/10;H03L7/093 主分类号 H03L7/10
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