| 摘要 |
A data processing apparatus comprises processing circuitry configured to perform processing operations; an instruction decoder responsive to program instructions to generate control signals for controlling said processing circuitry to perform said processing operations; wherein: said program instructions include at least one instruction specifying a control value having a first portion for indicating a selected data size selected from a plurality of data sizes and a second portion for indicating at least one control parameter having a number of bits that varies in dependence on said selected data size, said first portion and said second portion each having a variable number of bits; and said instruction decoder is responsive to said at least one instruction to generate control signals for controlling said processing circuitry to perform a corresponding processing operation in dependence on said selected data size and said at least one control parameter; wherein when processing said at least one instruction, at least one of said instruction decoder and said processing circuitry is configured to identify the number of bits comprised by said first portion of said control value and, in dependence on said number of bits comprised by said first portion, to identify (a) said selected data size, and (b) which bits of said control value form said second portion for indicating said at least one control parameter. |
