| 摘要 |
A method is provided for simulating leakage distribution of integrated circuit design. The method analyzes a layout of the integrated circuit design to understand the groups of dimensions of the transistors and capacitors of the layout, and then simulates a leakage distribution of the layout resulted from possible fabrication process variations. Therefore, designer can know the leakage distribution of the integrated circuit design before the integrated circuit design is actually fabricated, and modify the layout if a leakage failure happens to the layout.
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