发明名称 Cell arrangement method for designing semiconductor integrated circuit
摘要 Logic circuit information in which flip-flops of a semiconductor integrated circuit subjected to designing and a logic circuit between flip-flops are defined is input. The logic circuit information is analyzed to detect a logic circuit sandwiched by two flip-flops. The number of logic stages of the detected logic circuit is counted. It is determined, according to the counted number of logic stages, to which substrate potential a cell used for the logic circuit is to be connected.
申请公布号 US7861202(B2) 申请公布日期 2010.12.28
申请号 US20070798985 申请日期 2007.05.18
申请人 PANASONIC CORPORATION 发明人 SUMITA MASAYA
分类号 G06F17/50 主分类号 G06F17/50
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