发明名称 Stacked wafer level package and method manufacturing the same
摘要 <p>PURPOSE: A stacked wafer level package and a method for manufacturing the same are provided to reduce a cost for manufacturing the package by performing both a stacking process for semiconductor chips and a packaging process on a wafer. CONSTITUTION: An external connection unit is arranged in the lower part of a rearranged wiring layer(111). A chip connection pad(130a) is arranged on the upper part of the rearranged wiring layer. A semiconductor chip(160) is mounted on the rearranged wiring layer. A metal post(140) is electrically connected to the rearranged wiring layer. A sealing unit(170) hermetically seals the semiconductor chip. Electronic components(200) are electrically connected to the metal post.</p>
申请公布号 KR101003658(B1) 申请公布日期 2010.12.23
申请号 KR20080127091 申请日期 2008.12.15
申请人 发明人
分类号 H01L23/12 主分类号 H01L23/12
代理机构 代理人
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