发明名称 PLL circuit
摘要 A PLL circuit which can obtain a VCO output having satisfactory spurious output characteristics with respect to all channels and which can suppress the fluctuation of the characteristics due to a temperature change is disclosed. A control circuit 3 provides a frequency division ratio table 32 where frequency division ratios to improve spurious output characteristics in the output of a VCO for each channel number at temperatures are stored, and the control circuit reads, from the table 32, the frequency division ratio corresponding to the temperature detected by the temperature sensor 31 and an input channel number, to set the frequency division ratio in a PLL IC 2 and to set the channel number and the frequency division ratio in a DDS circuit 4. The DDS circuit 4 calculates the value of a reference frequency based on the channel number and the frequency division ratio to generate the reference frequency.
申请公布号 US2010315137(A1) 申请公布日期 2010.12.16
申请号 US20100801498 申请日期 2010.06.11
申请人 KIMURA HIROKI 发明人 KIMURA HIROKI
分类号 H03L7/08 主分类号 H03L7/08
代理机构 代理人
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