发明名称 MOUNTING METHOD OF ELECTRONIC COMPONENT, AND DESIGN METHOD OF SOLDER MASK
摘要 PROBLEM TO BE SOLVED: To provide a method capable of surely preventing the generation of a defective connection of solders and short circuits caused by the curvature of a substrate, and the like, without reducing the reliability and increasing the cost, when mounting electronic components which provide a plurality of terminals on a lower surface thereof to the substrate by reflow method. SOLUTION: When respective terminal and corresponding land are soldered by reflow method, in a state of oppositely arranging each of a number of terminals and a corresponding land, the amount of solder supplied between a terminal and a land facing with each other, individually increases/decreases, based on each distance between respective terminal and the corresponding land. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2010283080(A) 申请公布日期 2010.12.16
申请号 JP20090134302 申请日期 2009.06.03
申请人 FDK MODULE SYSTEM TECHNOLOGY CORP 发明人 SAKAYORI TAKASHI
分类号 H05K3/34;H01L21/60 主分类号 H05K3/34
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