| 摘要 |
<P>PROBLEM TO BE SOLVED: To further reduce clock skew between clock distribution networks. <P>SOLUTION: A clock distribution circuit includes, in association with each of a plurality of clock distribution networks, PLL circuits 1, 2 each for adjusting a phase of a reference clock signal 11 and distributing the reference clock signal to the clock distribution network; and feedback clock signal selection circuits 9, 16 for receiving feedback clock signals HA1-HAn, HB1-HBn respectively from a plurality of feedback points PA1-PAn, PB1-PBn in the clock distribution network and selecting one of the plurality of feedback signals, to be compared in phase, of the reference clock signal 11 in the PLL circuits 1, 2 based on delay values of the feedback clock signals. <P>COPYRIGHT: (C)2011,JPO&INPIT |
