| 摘要 |
<p>In a frequency dividing device, a 1/P frequency divider subjects an input clock signal to 1/P frequency division. A phase shifter shifts the phase of the 1/P frequency signal and outputs multiple different Q-phase signals. A switch controls phase shifting in accordance with a division ratio control signal, to switch the Q-phase signals from one to another. A 1/R frequency divider subjects the output from the switch to 1/R frequency division and outputs an Rth frequency clock signal. A 1/2 frequency divider subjects the Rth frequency clock signal to 1/2 frequency division and outputs a frequency divided clock signal. A division ratio setter receives a division ratio set signal and generates the division ratio control signal. As a division ratio, P×R×2-2×P/Q, P×R×2-P/Q, P×R×2, P×R×2+P/Q, and P×R×2+2×P/Q can be set.</p> |
