| 摘要 |
A data processing unit comprises scalar processor 101, heterogeneous processor (HPU) 102 which includes heterogeneous controller unit (HCU) 120, vector processing array 122 including a plurality of vector processors 123, low density parity-code (LDPC) accelerator unit 140a and fast Fourier transform (FFT) accelerator unit 140b. The scalar processor executes a series of instructions which include instructions which are customized for execution on the HPU which may be operable in a single instruction multiple data (SIMD) configuration. When the instructions for execution on the HPU are encountered they are automatically forwarded to HCU. The HCU includes instruction decode unit (150; fig 9) to decode instructions and forward them to one of a plurality of sequencers (1550-155N; figure 9) for execution on a corresponding function unit; each sequencer may include a FIFO instruction queue in storage (1540-154N; fig 9). The data processing unit is for a data processing system which may include a cluster of these data processing units (521-52N; fig 5). |
