发明名称 PERFORMING LOGIC OPTIMIZATION AND STATE-SPACE REDUCTION FOR HYBRID VERIFICATION
摘要 One embodiment of the present invention provides a system that facilitates optimization and verification of a circuit design. The system can receive a set of assumptions associated with a circuit. The set of assumptions can specify a set of logical constraints on at least a set of primary inputs of the circuit. Note that the set of assumptions are expected to be satisfied during normal circuit operation. The system can generate a stimulus generator based in part on an assumption in the set of assumptions. The output values from the stimulus generator, which when assigned to the set of primary inputs of the circuit, cause the set of primary inputs to satisfy the assumption. Next, the system can generate a modified circuit by coupling the outputs of the stimulus generator with a set of primary inputs of the circuit. The system can then perform logic optimization on the modified circuit to obtain an optimized circuit.
申请公布号 WO2010088102(A3) 申请公布日期 2010.11.25
申请号 WO2010US21429 申请日期 2010.01.19
申请人 SYNOPSYS, INC.;DSOUZA, ASHVIN M. 发明人 DSOUZA, ASHVIN M.
分类号 G06F19/00;G06F17/50 主分类号 G06F19/00
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