发明名称 MEMORY WITH BLOCK-ERASABLE LOCATIONS AND A LINKED CHAIN OF POINTERS TO LOCATE BLOCKS WITH POINTER INFORMATION
摘要 A memory apparatus has a main memory (10) that comprises a plurality of physical blocks of memory locations. The main memory (10), for example a flash memory, supports erasing of at least a physical block at a time. A chain of pointers (72, 75) that ultimately points to pointing information such as a logical address to physical address mapping table is stored in the main memory (10), each pointer (72, 75) being stored in a respective one of the blocks (70, 74), each non-final pointer (72) in the chain pointing to a respective block (74) that contains a next pointer in the chain. On start up of main memory (10) the pointing information is located by following said chain, using the pointers from the main memory. In normal operation direct pointers stored in a RAM are preferably used.
申请公布号 US2010299494(A1) 申请公布日期 2010.11.25
申请号 US20060158993 申请日期 2006.12.13
申请人 NXP B.V. 发明人 VAN ACHT VICTOR M.G.;LAMBERT NICOLAAS
分类号 G06F12/02 主分类号 G06F12/02
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