发明名称 FIGURE VERIFICATION METHOD AND DEVICE
摘要 <P>PROBLEM TO BE SOLVED: To very efficiently and quickly extract a hot spot, using a relative reference value (a first value) common to all the layers constituting an element, in a design stage, when manufacturing a highly reliable electronic device. <P>SOLUTION: A simulation figure of each design figure is prepared by performing exposure simulation on the design figure classified by a grouping part 2.A space and width of the prepared simulation figure are measured. A histogram is prepared for each design figure, based on the measured space and width of the simulation figure. The hot spot is determined based on the histogram, to correct a layout around the hot spot of the design figure. <P>COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2010257393(A) 申请公布日期 2010.11.11
申请号 JP20090109521 申请日期 2009.04.28
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 TSUJIMURA AKIRA
分类号 G06F17/50;H01L21/027;H01L21/82 主分类号 G06F17/50
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