发明名称 Speculative address translation for processor using segmentation and optional paging
摘要 An improved address translation method and mechanism for memory management in a computer system is disclosed. A segmentation mechanism employing segment registers maps virtual addresses into a linear address space. A paging mechanism optionally maps linear addresses into physical or real addresses. Independent protection of address spaces is provided at each level. Information about the state of real memory pages is kept in segment registers or a segment register cache potentially enabling real memory access to occur simultaneously with address calculation, thereby increasing performance of the computer system.
申请公布号 US7831799(B1) 申请公布日期 2010.11.09
申请号 US20040979499 申请日期 2004.11.01
申请人 BELGARD RICHARD 发明人 BELGARD RICHARD
分类号 G06F12/10 主分类号 G06F12/10
代理机构 代理人
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