| 摘要 |
<P>PROBLEM TO BE SOLVED: To minimize a duty-cycle error to reduce consumed power. <P>SOLUTION: A signal-frequency changing circuit comprises a delay line to delay a clock signal by a first delay time responsive to a delay-control signal for generating a delay signal, and to delay the clock signal by a smaller second delay time than the first delay time for generating a preliminary frequency-changing clock signal; a detector to generate a phase-fixture completion signal; a controller to subsequently shift the delay-control signal and a multiplex-control signal, by using the clock signal supplied until the time before reaching the actuating point of the phase-fixture completion signal; a multiplexer to select and output one of the preliminary frequency-changing clock signals in response to the multiplex-control signal; and an output unit to generate a frequency-changing clock signal having the frequency changed as different from the frequency of the clock signal, by using the clock signal and an output signal of the multiplexer. <P>COPYRIGHT: (C)2011,JPO&INPIT |
