| 摘要 |
<P>PROBLEM TO BE SOLVED: To accurately identify a fault spot of a delay fault in a fault diagnosis of a semiconductor integrated circuit. <P>SOLUTION: An extraction unit 116 of fault assumption and a finish-point flip-flop FF is provided, selects a fault assumption from fault assumption information, and implements a logic trace from the fault assumption toward an output side. A test result of a finish-point flip-flop FF is determined and obtained from a result of the trace from the fault assumption (117). The maximum value and the minimum value of a propagation path to the finish-point flip flop FF are obtained. A delay range is obtained from them. A delay range is obtained by using the delay margin and the test result obtained in 117 (118). A fault candidate and the delay range of the delay fault are identified by a fault candidate/delay range determination section 119. <P>COPYRIGHT: (C)2011,JPO&INPIT |
