发明名称 Power-rail ESD protection circuit with ultra low gate leakage
摘要 An ESD protection circuit including a clamping module and a detecting module is provided. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a MOS capacitor. An output terminal of the triggering unit is used for triggering the clamping module. The resistor is coupled between the negative power line and an input terminal of the triggering unit. The MOS capacitor is coupled between the positive power line and an input terminal of the triggering unit for ESD protection. During a normal power operation, a switching terminal of the triggering unit enables the MOS capacitor to be coupled between the negative power line and an input terminal of the triggering unit. Thereby, the gate tunneling leakage is eliminated and the problem of mistriggering is prevented.
申请公布号 US7817390(B2) 申请公布日期 2010.10.19
申请号 US20090461237 申请日期 2009.08.05
申请人 AMAZING MICROELECTRONIC CORP. 发明人 KER MING-DOU;CHEN CHIN-HAO;JIANG RYAN HSIN-CHIN
分类号 H02H9/04 主分类号 H02H9/04
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