发明名称 |
Pipeline processing communicating adjacent stages and controls to prevent the address information from being overwritten |
摘要 |
A bus apparatus for transferring information between a bus master and a bus slave includes a plurality of pipeline registers capable of transmitting information from the bus master to the bus slave by a pipeline processing; and a plurality of management devices that manage each pipeline register. Also, the management device includes: a holding state keeping unit that keeps a holding state as information indicating whether a current stage's pipeline register corresponding to the management device holds information; an adjacent stage's holding state specifying unit that specifies the holding state of a previous stage's pipeline register that transmits information to the current stage's pipeline register and the holding state of a subsequent stage's pipeline register to which information from the current stage's pipeline register is transmitted; and a transfer control unit that determines whether information held by the corresponding pipeline register is transferred.
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申请公布号 |
US7818546(B2) |
申请公布日期 |
2010.10.19 |
申请号 |
US20060517327 |
申请日期 |
2006.09.08 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
ASANO SHIGEHIRO;YOSHIKAWA TAKASHI |
分类号 |
G06F9/00;G06F7/38;G06F9/44;G06F13/00 |
主分类号 |
G06F9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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