发明名称 ROW OF FLOATING POINT ACCUMULATORS COUPLED TO RESPECTIVE PES IN UPPERMOST ROW OF PE ARRAY FOR PERFORMING ADDITION OPERATION
摘要 Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support floating-point operations, the parallel processor uses floating-point accumulators and a flag for floating-point multiplication. Using the parallel processor, it is possible to process a geometric transformation operation in a 3-dimensional (3D) graphics process at low cost. Also, the cost of a bus width for instructions can be minimized by a partitioned Single-Instruction Multiple-Data (SIMD) method and a method of conditionally executing instructions.
申请公布号 US2010257342(A1) 申请公布日期 2010.10.07
申请号 US20100817407 申请日期 2010.06.17
申请人 ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE 发明人 LYUH CHUN GI;YANG YIL SUK;HEO SE WAN;YEO SOON IL;ROH TAE MOON;KIM JONG DAE;KIM KI CHUL;YOO SE HOON
分类号 G06F9/302 主分类号 G06F9/302
代理机构 代理人
主权项
地址