| 摘要 |
PROBLEM TO BE SOLVED: To provide a self-synchronous type scramble processing circuit which releases delay time caused by an exclusive OR gate and is used by 40G/100G-Ethernet(R) or the like for which high throughput is required. SOLUTION: The scramble processing circuit performs addition processing of partial exclusive OR to the unscrambled data before performing scramble processing, holds addition-processed data, holds scrambled data scramble-processed one clock before, performs addition processing of the exclusive OR of addition-processed data held by an addition processing/data holding section and the scrambled data of one clock before held by a scrambled data holding section, and generates the desired scrambled data. COPYRIGHT: (C)2011,JPO&INPIT
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