CLOCK GENERATORS, MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR PROVIDING AN INTERNAL CLOCK SIGNAL

摘要

A clock generator includes a first input end and a second input end. The first input end is capable of receiving a first clock signal including a first state transition and a second state transition defining a first pulse width. The second input end is capable of receiving a second clock signal having a third state transition. A time period ranges from the first state transition to the third state transition. The clock generator can compare the first pulse width and the time period. The clock generator can output a third clock signal having a second pulse width ranging from a fourth state transition to a fifth state transition. The fifth state transition of the third clock signal is capable of being triggered by the second state transition of the first clock signal or the third state transition of the second clock signal depending on the comparison of the first pulse width and the time period.