| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an integrated circuit memory element that compensate for the differences in total line resistance of memory cells at different locations of a memory cell array; and to provide a data storage device and an electronic system including the same. <P>SOLUTION: The integrated circuit memory device 10 includes a memory cell array 100 including memory cells 105 having respective data storage regions therein, a plurality of pass transistors having different channel widths and/or channel lengths, and a plurality of conductive lines each electrically coupling a respective one of the pass transistors to ones of the memory cells. Each of the memory cells has a line resistance defined by a portion of the corresponding one of the conductive lines extending between the memory cell and the pass transistor coupled thereto. Ones of the memory cells having greater line resistances are coupled to ones of the pass transistors having great channel widths and/or short channel lengths. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
