发明名称 SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME
摘要 PROBLEM TO BE SOLVED: To apply optimal stress to each of an N-type transistor and a P-type transistor, in a semiconductor device including an N-type MIS-FET and a P-type MIS-FET. SOLUTION: In first insulation regions 101 being element isolation regions, second insulation regions 107 for providing tensile stress to the circumference and third insulation regions 108 for providing compressive stress to the circumference are formed. The second insulation regions 107 and the third insulation regions 108 are arranged for the N-type MIS-FET 50 to respectively provide tensile stress to the circumference of a first active region 103 in directions vertical to and parallel to a moving direction of electrons, and arranged for the P-type MIS-FET 60 to provide compressive stress to the circumference of a second active region 104 in a direction parallel to a moving direction of holes and provide tensile stress thereto in the direction vertical to the moving direction of the holes. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010219440(A) 申请公布日期 2010.09.30
申请号 JP20090066884 申请日期 2009.03.18
申请人 PANASONIC CORP 发明人 UEDA KENJI
分类号 H01L21/8238;H01L21/76;H01L27/08;H01L27/092 主分类号 H01L21/8238
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