| 摘要 |
PROBLEM TO BE SOLVED: To actualize a desired delay time, miniaturize a delay circuit, and reduce power consumption in a protection circuit. SOLUTION: The delay circuit 100 includes a first inverter 101 to a third inverter 103, a fourth p channel MOSFET 7, a fourth n channel MOSFET 8, a delay resistor 121, and a capacitor 122. The delay resistor 121 is connected between an output terminal of the first inverter 101 and an input terminal of the second inverter 102. A gate terminal of the fourth n channel MOSFET 8 is connected to a node 113 located between the delay resistor 121 and the input terminals of the second inverter 102. The capacitor 122 is connected between the gate terminal and a drain terminal of the fourth n channel MOSFET 8. Capacity of the capacitor 122 is enlarged in false to an extent larger than physical electrostatic capacity of the capacitor 122, using feedback capacity of the fourth n channel MOSFET 8. COPYRIGHT: (C)2010,JPO&INPIT
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