发明名称 DEBUGGING SIMULATION WITH PARTIAL DESIGN REPLAY
摘要 A virtual platform simulates behavior of a modular circuit based on a circuit design including both high-level and low-level models of circuit modules. A compiler that converts the high-level and low-level models into executable models prior to an initial simulation also generates a separate “replay engine” corresponding to each low-level module for use during subsequent replay simulations. During the initial simulation, the virtual platform simulates circuit behavior by concurrently executing the high-level and low-level executable models and recording data representing behavior of output signals of the low-level design modules modeled by the executable models. To speed up subsequent replays of the simulation, the virtual platform executes one or more of the replay engines in lieu of executing their corresponding low-level executable models. Each executed replay engine simulates behavior of each output signal of a corresponding low-level module in response to the data recorded during the initial simulation representing the behavior of that output signal.
申请公布号 US2010241414(A1) 申请公布日期 2010.09.23
申请号 US20090407169 申请日期 2009.03.19
申请人 SPRINGSOFT USA, INC. 发明人 YEH NAN-TING;CHENG WENCHU;TSAI KUEN-YANG;HO CHIA-LING
分类号 G06F17/50 主分类号 G06F17/50
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