| 摘要 |
Data processing apparatus comprising a processor 10 and a cache memory 32 having a plurality of cache lines. A cache controller 34 is also provided comprising: preload circuitry 35 storing data values from a main memory into cache-lines operable in response to a streaming preload instruction received at the processor; identification circuitry 36 operable in response to the streaming preload instruction to identify cache lines for preferential reuse (for example by setting a valid bit associated with the cache line); cache maintenance circuitry 37 to select cache lines for reuse having regard to any preferred for reuse identification generated by the identification circuitry. In this way, a single streaming preload instruction can be used to trigger both a preload of cache lines of data values into the cache memory, and also to mark for preferential reuse other cache lines of the cache memory. Data values can be stored in cache lines following the current line address for preload or preceding said current address for reuse. The cache memory can be n-way set associative.
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