| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a phase locked loop circuit in which fractional spurious is not produced. <P>SOLUTION: In a phase locked loop circuit which obtains an output signal coincident in frequency and phase with a target signal which is obtained by multiplying the frequency of a reference signal by a ratio represented by the sum of a first fraction and a second fraction, the circuit includes: a controlled oscillator 120 including the same number of stages of annularly connected amplifiers as a number which is obtained by dividing, by 2, the least common multiple of a denominator of the first fraction, a denominator of the second fraction and 2, the same number of multiphase signals as the least common multiple being extractable from the controlled oscillator, the frequency of the multiphase signals being controlled by a digital control signal and an analog control signal, and one of the multiphase signals being output as the output signal; a conversion part 116 which converts frequency difference and phase difference between the output signal and the reference signal into a digital signal; and a signal selection part 140 which sequentially selects signals coincident in the phase with the reference signal in the next cycle from the multiphase signals at each cycle of the reference signal in accordance with the digital signal. <P>COPYRIGHT: (C)2010,JPO&INPIT |
