发明名称 |
Memory having an ECC system |
摘要 |
An error correction code system for a memory having parity columns of a memory array located within the memory array is provided. The parity columns are grouped together or distributed throughout the memory array. An embodiment includes a multiplexor circuit for selectively coupling only parity bits stored in the parity memory array to I/O circuitry, bypassing ECC logic circuitry and allowing the parity columns to be directly accessible, in a direct access mode or for selectively coupling the parity bits to ECC logic circuitry in an ECC mode.
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申请公布号 |
US7779334(B2) |
申请公布日期 |
2010.08.17 |
申请号 |
US20070767689 |
申请日期 |
2007.06.25 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
EARLE ADRIAN;RAO RAVIPRAKRASH S.;JOSHI VINEET |
分类号 |
G11C29/00 |
主分类号 |
G11C29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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