发明名称 OUTPUT BUFFER HAVING PREDRIVER FOR COMPENSATING SLEW RATE AGAINST PROCESS VARIATION
摘要 <P>PROBLEM TO BE SOLVED: To provide an output buffer incorporating a compensation circuit and a predriver and having a slew rate which is compensated against process variations. Ž<P>SOLUTION: A compensation circuit 370 includes an operational amplifier 250, a second NFET 240, a third NFET 371 having a gate connected to an output of the amplifier, and an execution resistance 381. In an output buffer 300, the core 150 of an IC chip asserts a control signal to a predriver 310. In response thereto, the predriver 310 asserts the control signal buffered in a first NFET 320, turns on the first NFET 320, and asserts an output signal of a VSS level to a pad 230. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2010178346(A) 申请公布日期 2010.08.12
申请号 JP20100025455 申请日期 2010.02.08
申请人 ALTERA CORP 发明人 RANJAN NALINI;YANG HENRY
分类号 G05F3/24;H03K19/0175;H01L21/822;H01L27/04;H03F1/30;H03F3/345;H03F3/347;H03F3/45;H03K17/687;H03K19/003 主分类号 G05F3/24
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