发明名称 |
Structure and method of mapping signal intensity to surface voltage for integrated circuit inspection |
摘要 |
Embodiments of the present invention provide a test structure for inspection of integrated circuits. The test structure may be fabricated on a semiconductor wafer together with one or more integrated circuits. The test structure may include a common reference point for voltage reference; a plurality of voltage dropping devices being connected to the common reference point; and a plurality of electron-collecting pads being connected, respectively, to a plurality of contact points of the plurality of voltage dropping devices. A brightness shown by the plurality of electron-collecting pads during an inspection of the integrated circuits may be associated with a pre-determined voltage.
|
申请公布号 |
US7772866(B2) |
申请公布日期 |
2010.08.10 |
申请号 |
US20070683058 |
申请日期 |
2007.03.07 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION;SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
PATTERSON OLIVER D.;WILDMAN HORATIO SEYMOUR;SUN MIN-CHUL |
分类号 |
G01R31/02 |
主分类号 |
G01R31/02 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|