发明名称 |
Dual-issuance of microprocessor instructions using dual dependency matrices |
摘要 |
A dual-issue instruction is decoded to determine a plurality of LSU dependencies needed by an LSU part of the dual-issue instruction and a plurality of non-LSU dependencies needed by a non-LSU part of the dual-issue instruction. During dispatch of the dual-issue instruction by the microprocessor, the dual dependency matrices are employed as follows: a Load-Store Unit (LSU) dependency matrix is written with the plurality of LSU dependencies and a non-LSU dependency matrix is written with the plurality of non-LSU dependencies; an LSU issue valid (LSU IV) indicator is set as valid to issue; an LSU portion of the dual-issue instruction is issued once the plurality of LSU dependencies of the dual issue instruction are satisfied; a non-LSU issue valid (non-LSU IV) indicator is set as valid to issue; and a non-LSU portion of the dual-issue instruction is issued once the plurality of non-LSU dependencies of the dual issue instruction are satisfied. The LSU dependency matrix and the non-LSU dependency matrix can then be notified that one or more instructions dependent upon the dual-issue instruction may now issue.
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申请公布号 |
US7769984(B2) |
申请公布日期 |
2010.08.03 |
申请号 |
US20080208683 |
申请日期 |
2008.09.11 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ALEXANDER GREGORY W.;BARRICK BRIAN D.;EISEN LEE E.;WARD, III JOHN W. |
分类号 |
G06F9/30;G06F9/40;G06F15/00 |
主分类号 |
G06F9/30 |
代理机构 |
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