发明名称 |
Memory controller operating in a system with a variable system clock |
摘要 |
The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access.
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申请公布号 |
US7761682(B2) |
申请公布日期 |
2010.07.20 |
申请号 |
US20080191195 |
申请日期 |
2008.08.13 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BARNUM MELISSA ANN;BELLOWS MARK DAVID;GANFIELD PAUL ALLEN;LAMBRECHT LONNY;OZGUNER TOLGA |
分类号 |
G06F13/14;G06F13/36 |
主分类号 |
G06F13/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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