| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory cell array of which the size can be reduced and density can be increased, and which is compatible with existing semiconductor manufacturing technology. SOLUTION: The memory cell array 10 is formed by arranging a plurality of memory cells 100 in an array. The memory cell 100 includes a MOS transistor 110, and a nano gap element 120 having a first electrode 113 connected to one diffusion layer 112a of the MOS transistor 110 and formed in a contact hole 101a. The nano gap element 120 has a clearance of a nano meter order in which a change phenomenon of a resistance value occurs when a predetermined voltage is applied between a first conductor 121 and a second conductor 122 arranged above the first conductor 121. A word line WL is connected to a gate region 115 of the MOS transistor 110. A first bit line BL1 is connected to a second electrode 114 connected to other diffusion layer 112b of the MOS transistor 110. The second bit line BL2 is connected to the second conductor 122. COPYRIGHT: (C)2010,JPO&INPIT |
