发明名称 Semiconductor Device with Reduced Parasitic Inductance
摘要 The present invention provides a technology for reducing the parasitic inductance of the main circuit of a power source unit. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETs, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are
申请公布号 US2010176430(A1) 申请公布日期 2010.07.15
申请号 US20100721201 申请日期 2010.03.10
申请人 RENESAS TECHNOLOGY CORP. 发明人 HASHIMOTO TAKAYUKI;AKIYAMA NOBORU;SHIRAISHI MASAKI;KAWASHIMA TETSUYA
分类号 H01L27/06 主分类号 H01L27/06
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