发明名称 SYNCHRONIZATION CIRCUIT
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a synchronization circuit capable of preventing a rewriting of a control value with a fixed value of an isolation cell, and not increasing standby current. <P>SOLUTION: The synchronization circuit 1 includes: an internal partial power-off circuit 11 capable of cutting the power off; an internal partial power-off control circuit 12 for conducting control of the power-off; and isolation cells 13, 14 for outputting the output from the internal partial power-off circuit 11 as the fixed value, when the internal partial power-off circuit 11 is powered off. The internal partial power-off circuit 11 includes: a data transmitting register 22 for outputting data for controlling the power-off; and a clock enable control register 24 for outputting an enable signal. The internal partial power-off control circuit 12 includes: a gated clock buffer 25 for control the clock on the basis of the enable signal; and a data receiving register 26 for importing data on the basis of the controlled clock. <P>COPYRIGHT: (C)2010,JPO&INPIT</p>
申请公布号 JP2010154294(A) 申请公布日期 2010.07.08
申请号 JP20080330837 申请日期 2008.12.25
申请人 TOSHIBA CORP 发明人 KAJIWARA HIROTSUGU
分类号 H03K19/00;G06F1/04;G06F1/12;H03K5/00;H03K19/0175 主分类号 H03K19/00
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