发明名称 Processing packet streams
摘要 <p>A system for processing packet streams, the system comprising: a system data-bus for transferring packets of data; a system memory connected to the data-bus for storing packets; a first processor connected to the data-bus, arranged to retrieve secure packets from the system memory via the data-bus; and a second processor connected to the data-bus, programmed to perform security processing by applying one or more security algorithms to the secure packets to generate at least partially security-processed packets. The first processor is programmed so as to control the security processing of a previously retrieved packet by the second processor, the security processing involving a delay whilst the first processor awaits the return of a security-processed packet from the second processor; and the first processor is arranged to further process a previously security-processed packet to generate a corresponding output data during the delay.</p>
申请公布号 EP2204997(A2) 申请公布日期 2010.07.07
申请号 EP20090179044 申请日期 2009.12.14
申请人 STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED 发明人 BOLTON, MARTIN;PEARSON, PAUL;EMSLIE, DIARMUID
分类号 H04N7/24;H04N5/00 主分类号 H04N7/24
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