| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a flash EEPROM that comprises memory cell transistors and selection transistors and suppresses a gate induced drain leak current (GIDL). <P>SOLUTION: The method includes: introducing impurities in a direction inclined with respect to the surface of a semiconductor substrate and parallel to a gate length direction of the memory cell transistor CT and selection transistor ST; introducing impurities in a direction inclined with respect to the surface of the semiconductor substrate that has been rotated by a given angle with respect to a horizontal direction, and intersecting with the gate length direction of the memory cell transistor and the selection transistor; and forming source and drain diffusion layers of the memory cell transistor and the selection transistor such that an impurity concentration in the substrate surface in between the gate electrode of the memory cell transistor and the gate electrode of the selection transistor is lower than the impurity concentration in the substrate surface in between gate electrodes of the memory cell transistors and the impurity concentration in the substrate surface in between gate electrodes of the selection transistors. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
