发明名称 |
State retention for formal verification |
摘要 |
Verification model of static state retention behavior of a state saving element design during power shut off of the state saving element in an integrated circuit design including: creating in a computer readable medium a model of a single edge triggered state saving element; and creating in the computer readable medium clock gate logic that suspends saving of new states by the single state saving element upon the occurrence of a first state retention signal in preparation for power shut off.
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申请公布号 |
US7747971(B1) |
申请公布日期 |
2010.06.29 |
申请号 |
US20070772118 |
申请日期 |
2007.06.30 |
申请人 |
CADENCE DESIGN SYSTEMS, INC. |
发明人 |
CHOPRA MANU;JAIN ALOK;MARSCHNER ERICH |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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