| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device which is improved in a disturb margin while maintaining a right margin. <P>SOLUTION: A memory cell array 1 is configured by disposing a memory cell MC including one pair of cross-connected inverters INV1 and INV2 at each intersection of word lines WL and bit lines BL, /BL. Dummy transistors QND1-2 have a threshold voltage which has a certain relationship with a threshold voltage of the transistor which configures the memory cell MC. A dummy bit line DBL is connected to one end of a dummy transistor DBL and charged to have a predetermined potential. A word line driver 2 changes a rise time of the voltage of the word line WL in accordance with a change in a voltage of the dummy bit line DBL. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
