发明名称 CLOCK GENERATING DEVICE, INTEGRATED CIRCUIT DEVICE, ELECTRONIC DEVICE AND METHOD OF GENERATING CLOCK
摘要 <P>PROBLEM TO BE SOLVED: To provide a clock generating device or the like for reducing power consumption during a normal operation when testing circuit blocks operated by clocks different from each other by a single test clock. Ž<P>SOLUTION: The clock generating device for generating an operation clock in a second operation mode for first and second circuit blocks 30 and 50 operated in synchronism with first and second clocks CLK1 and CLK2 in a first operation mode includes a phase adjustment circuit for generating a first phase adjustment clock by adjusting the phase of the first clock CLK1 supplied to a first clock line whose delay amount is larger than that of a second clock line to which the second clock CLK2 is supplied and a clock stop control circuit for stopping the input of the first clock CLK1 to the phase adjustment circuit in the first operation mode, wherein the second clock CLK2 in the first operation mode and the first phase adjustment clock in the second operation mode are output to the second circuit block 50, respectively. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2010141388(A) 申请公布日期 2010.06.24
申请号 JP20080312998 申请日期 2008.12.09
申请人 SEIKO EPSON CORP 发明人 KUWAZAWA ATSUSHI
分类号 H03K5/00;G01R31/28;H01L21/822;H01L27/04 主分类号 H03K5/00
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