Circuit device to produce an output signal including dither

摘要

In a particular embodiment, a circuit device includes a count zero circuit having a first counter to receive a clock signal and to produce a count zero signal based on the clock signal and having a second counter to generate a reset control signal to control a reset of the count zero circuit. The circuit device further includes a turnoff circuit to receive the clock signal and to produce a turn off signal based on the clock signal. Further, the circuit device includes a pulse width modulated (PWM) latch circuit adapted to produce a gate drive signal based on the count zero signal and the turn off signal, where timing of an edge of the gate drive signal varies based on the reset control signal.